1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, the invention relates to a method of forming a gate electrode of a MOSFET by the use of a photolithographic process and an etching process.
2. Description of the Background Art
FIGS. 27 through 33 show a background art method of manufacturing a semiconductor device in order of process steps. In FIGS. 27 through 33, top plan views are labelled (A), and sectional views showing sectional structures taken along a line X100xe2x80x94X100 in the top plan views are labelled (B).
With reference to FIG. 27, an impurity is initially introduced into an upper surface of a silicon substrate 101 to form a well 102. In this step, a p well is formed when a p type impurity such as phosphorus is introduced, and an n well is formed when an n type impurity such as boron is introduced. Next, a trench-type isolating insulation film 103 made of silicon oxide or the like is partially formed in the upper surface of the silicon substrate 101 by a known trench isolation technique. Referring to the top plan view labelled (A) in FIG. 27, a portion in which the isolating insulation film 103 is not formed serves as a device formation region for formation of a MOSFET. In other words, the device formation region is defined by the isolating insulation film 103.
Referring to FIG. 28, a silicon oxide film 104 is formed entirely on the well 102 and the isolating insulation film 103 by a CVD process using TEOS (Tetra Ethyl Ortho Silicate) as a source gas. Next, a polysilicon film 105 is formed entirely on the silicon oxide film 104 by a CVD process. Then, a silicon oxide film 106 is formed entirely on the polysilicon film 105 by a thermal oxidation process or a CVD process using TEOS as a source gas. Next, a negative photoresist 107 is applied entirely onto the silicon oxide film 106.
Referring to FIG. 29, the photoresist 107 is exposed to light using a photomask 110 having a pattern in which openings 111 (designated by the reference characters 111i to 111k in FIG. 29) are formed over respective regions wherein gate electrodes are to be formed, that is, using the photomask 110 having an opening pattern similar to a gate electrode layout pattern. The photomask 110 has a structure such that a light shielding film 109 is formed on a glass substrate 108. With reference to the top plan view labelled (A) in FIG. 29, the photomask 110 has a plurality of (in this case, as an example, three) openings 111i to 111k formed therein. The openings 111i and 111j are arranged adjacent to each other on the same line extending in a direction of a gate width (in the vertical direction of the figure).
FIG. 30 shows the photoresist 107 after being exposed to light in the step shown in FIG. 29. With reference to the top plan view labelled (A) in FIG. 30, the photoresist 107 has exposed portions 112 (designated by the reference characters 112i to 112k in FIG. 30) formed in corresponding relation to the openings 111 of the photomask 110.
Referring to FIG. 31, a portion (or an unexposed portion) of the photoresist 107 which is not exposed to light in the step shown in FIG. 29 or a portion of the photoresist 107 other than the exposed portions 112 is removed by development. Thus, only photoresists 113 (designated by the reference characters 113i to 113k in FIG. 31) corresponding to the exposed portions 112 are left on the silicon oxide film 106.
Referring to FIG. 32, the silicon oxide film 106 is patterned using the photoresists 113. More specifically, using the photoresists 113 as an etch mask, the silicon oxide film 106 is etched by an anisotropic dry etching process which exhibits a higher etch rate in a direction of depth of the silicon substrate 101. This removes a portion of the silicon oxide film 106 which is not covered with the photoresists 113, to expose an upper surface of the polysilicon film 105 under the portion. Only silicon oxide films 114 (designated by the reference characters 114i to 114k in FIG. 32) corresponding to the portions of the entirely formed silicon oxide film 106 which are covered with the photoresists 113 are left on the polysilicon film 105. Thereafter, the photoresists 113 are removed.
Referring to FIG. 33, using the silicon oxide films 114 as an etch mask (hard mask), the polysilicon film 105 and the silicon oxide film 104 are etched in the order named by an anisotropic dry etching process which exhibits a higher etch rate in the direction of depth of the silicon substrate 101. This removes portions of the polysilicon film 105 and the silicon oxide film 104 which are not covered with the silicon oxide films 114, to expose upper surfaces of the well 102 and the isolating insulation film 103 under the portions. With reference to the sectional view labelled (B) in FIG. 33, a gate structure 117 (designated by the reference character 117k in FIG. 33) having a multi-layer structure such that a silicon oxide film 116k, a polysilicon film 115k and the silicon oxide film 114k are stacked in the order named is formed on the well 102. The silicon oxide film 116k functions as a gate insulation film, and the polysilicon film 115k functions as a gate electrode. With reference to the top plan view labelled (A) in FIG. 33, gate structures 117i and 117j each having a multi-layer structure similar to the gate structure 117k are formed on the well 102 and the isolating insulation film 103. The reference numeral 117 is also used hereinafter to generically designate the gate structures 117i, 117j and 117k. 
Thereafter, a silicon oxide film is formed entirely on the top surface by a CVD process, and is etched back by an anisotropic etching process, thereby forming sidewalls on the side surfaces of each of the gate structures 117. Next, an impurity is introduced into the upper surface of the well 102 by an ion implantation process to form a pair of source/drain regions on opposite sides of each of the gate structures 117. MOSFETs are formed by the above-mentioned process steps. Then, an interconnection step is performed, and a semiconductor device is thus completed.
In the background art method of manufacturing the semiconductor device as described above, the photoresist 107 is exposed to light in the step shown in FIG. 29, using the photomask 110 having the opening pattern similar to the gate electrode layout pattern. The photoresist 107 is developed to produce the photoresists 113, and the silicon oxide film 106 is patterned using the photoresists 113 to form the silicon oxide films 114. Then, etching is performed using the silicon oxide films 114 as a hard mask to form the gate structures 117.
Unfortunately, when the photoresist 107 is exposed to light in the step shown in FIG. 29, corners of the openings 111 are influenced by interference of light, which results in rounded corners of the exposed portions 112, as shown in FIG. 30. When a dimension of the openings 111 as measured in a direction of a gate length (in the horizontal direction in the figures) decreases with the decreasing size of the semiconductor device, a dimension of the exposed portions 112 becomes less than a dimension of the openings 111, as measured in the direction of the gate width. Since the shape of the exposed portions 112 is reflected finally in the shape of the gate structures 117, a finished dimension of the gate structures 117 is less than the dimension of the openings 111, as measured in the direction of the gate width. Thus, the background art method of manufacturing the semiconductor device has a problem such that the finished shape of the gate structures 117 recedes from the shape of the openings 111 of the photomask 110, as seen in the direction of the gate width, which results from the use of the single photomask 110 having the opening pattern similar to the gate electrode layout pattern for the exposure of the photoresist 107 to light. Such a problem deteriorates the performance of the MOSFETs because of variations in finished shape of the gate structures 117, or hinders the increase in level of integration of a semiconductor integrated circuit.
To solve the problem, a technique can be contemplated for designing a slightly greater dimension of the openings 111 as measured in the direction of the gate width, based on the predicted amount of receding of the gate structures 117. However, the prediction of the amount of receding requires repeated experiments. Additionally, when the openings 111i and 111j are adjacent to each other in the direction of the gate width as shown in FIG. 29, there is a limit to the amount of increase in the width of the openings 111i and 111j. Thus, this technique does not radically solve the problem with the background art method of manufacturing the semiconductor device.
It is an object of the present invention to provide a method of manufacturing a semiconductor device which can avoid the receding of the shape of a gate structure from the shape of an opening of a photomask, thereby forming the gate structure having dimensions as designed.
According to a first aspect of the present invention, the method of manufacturing a semiconductor device includes the following steps (a) to (l). The step (a) prepares a semiconductor substrate. The step (b) forms a first film on the semiconductor substrate, the first film being electrically conductive. The step (c) forms a second film on the first film. The step (d) forms a first photoresist on the second film. The step (e) exposes the first photoresist to light using a first photomask having a first pattern. The step (f) develops the first photoresist exposed in the step (e). The step (g) patterns the second film using the first photoresist developed in the step (f) to form a third film over a region in which a gate electrode is to be formed, the third film being wider than a gate width of the gate electrode. The step (h) is executed after the step (g). The step (h) forms a second photoresist on the first film to cover the third film. The step (i) exposes the second photoresist to light using a second photomask having a second pattern defining an end of the gate electrode as seen in a direction of the gate width. The step (j) develops the second photoresist exposed in the step (i). The step (k) patterns the third film using the second photoresist developed in the step (j) to form a fourth film. The step (l) etches the first film using the fourth film as an etch mask to form the gate electrode.
In the method, the third film wider than the gate width of the gate electrode is formed, and thereafter the end of the third film is removed to form the fourth film. Using the fourth film as an etch mask, the first film is etched to form the gate electrode. Therefore, the method can correctly set the gate width of the gate electrode.
According to a second aspect of the present invention, the method of manufacturing a semiconductor device includes the following steps (a) to (l). The step (a) prepares a semiconductor substrate. The step (b) forms a first film on the semiconductor substrate, the first film being electrically conductive. The step (c) forms a second film on the first film. The step (d) forms a first photoresist on the second film. The step (e) exposes the first photoresist to light using a first photomask having a first pattern. The step (f) develops the first photoresist exposed in the step (e). The step (g) patterns the second film using the first photoresist developed in the step (f) to form a third film extending continuously from over a region in which a first gate electrode is to be formed to over a region in which a second gate electrode is to be formed, the first gate electrode and the second gate electrode being arranged adjacent to each other in a direction of a gate width. The step (h) is executed after the step (g). The step (h) forms a second photoresist on the first film to cover the third film. The step (i) exposes the second photoresist to light using a second photomask having a second pattern defining an end of the first gate electrode which is closer to the second gate electrode and an end of the second gate electrode which is closer to the first gate electrode. The step (j) develops the second photoresist exposed in the step (i). The step (k) patterns the third film using the second photoresist developed in the step (j) to form a fourth film. The step (l) etches the first film using the fourth film as an etch mask to form the first and second gate electrodes.
In the method, the third film is formed extending continuously from over the region in which the first gate electrode is to be formed to over the region in which the second gate electrode is to be formed, and is then patterned to form the fourth film. Using the fourth film as an etch mask, the first film is etched to form the first and second gate electrodes. This allows a distance between the first and second gate electrodes to be set to a minimum line width. Consequently, a high level of integration of the semiconductor device is achieved.
Preferably, the method further includes the following step (m). The step (m) is executed after the step (g). The step (m) thins the third film by etching.
The method provides a shorter gate length of the finally obtained gate electrode to achieve a higher speed operation of the semiconductor device.
Preferably, the step (m) is executed before the step (k).
The method can avoid gate width variations resulting from etching of the fourth film in an isotropic etching process for thinning the third film.
Preferably, the method is applied to formation of gate electrodes of respective transistors constituting an SRAM memory cell.
The method can achieve the size reduction of the SRAM memory cell.
Preferably, the method is applied to formation of gate electrodes of respective memory cell transistors in a memory cell array.
The method can achieve the size reduction of the memory cell array.
Preferably, the method is applied to formation of gate electrodes of respective transistors in a macrocell region.
The method can achieve the size reduction of the macrocell region.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.